Advanced R&D Analog Design Engineer

Position

Vollzeit

Festanstellung

Mid

Ingenieurwesen

Konditionen

St-Sulpice VD, Waadt

100%

Anforderungen

5+ J. Erfahrung

Master

EU/EFTA-Bewilligung

Skills

Cadence VirtuosoLayout designSpectreHigh-precision circuit designParasitic extractionEM and IR drop analysisAnalog designfunctional test benchesHigh-speed signal conditioningECAD toolsCalibroDesign rule checks (DRC)

Sprachen

Englisch

Französisch

Beschreibung

Job Title: Analog Design Engineer (Advanced Research and Development Department)

Key responsibilities:

Develop block level specifications and models for target designs
Develop, model, design, and verify performance of custom analog circuits in advanced technology nodes
Layout design and development, including floor-planning, guiding layout engineers, and post-layout verification
Design verification at different levels (pre- and post-layout, variation-aware)
Support and collaborate with the design team, including other design and layout engineers, architects and chip level integration engineers, modeling and system level designers.
Support for post-silicon lab bring-up, debug, characterization and productization.
Produce reports (progress report, analysis, design, modeling, and verification reports)
Participate in developing concept level architectures and circuits

Aufgaben

Develop block level specifications and models for target designs
Develop, model, design, and verify performance of custom analog circuits in advanced technology nodes
Layout design and development, including floor-planning, guiding layout engineers, and post-layout verification
Design verification at different levels (pre- and post-layout, variation-aware)
Support and collaborate with the design team, including other design and layout engineers, architects and chip level integration engineers, modeling and system level designers
Support for post-silicon lab bring-up, debug, characterization and productization
Produce reports (progress report, analysis, design, modeling, and verification reports)
Participate in developing concept level architectures and circuits

Anforderungen

Deep understanding on design and layout techniques for high-speed and high-precision circuits
Experience in developing testbenches and simulation setups to analyze performance of target circuits and systems
Skillful in layout techniques, such as matching, parasitic estimation and reduction, and deep-submicron related issues
Advanced user of EDA tool for design and verification, preferably Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitic extraction and modelling, EM and IR drop tools, and ESD analysis
Self-motivated, with strong sense of ownership and responsibility
Manage workload, schedules and report to internal management and technical teams
Excellent communication and reporting skills
5+ years of experience in design and layout of analog and mixed-signal circuits, especially high-speed and high-precision circuits
MSc or PhD in electronics/electrical engineering (equivalent or higher)
Experienced with modern semiconductor process technologies, such as CMOS 28nm, and FinFET 16/14nm, 7nm
Experienced in high-level modelling, top-level simulations, and signal integrity
Solid background on Signal Processing and Communications

Technologien

Cadence VirtuosoSpectre/HSpiceCalibre/PVS DRC/LVS

Unternehmen

Kandou Bus SA

Semiconductors

At Kandou, we are redeﬁning the economics of AI infrastructure. Our mission is to democratise AI by signiﬁcantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption. Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption signiﬁcantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale. Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.